Start with simple key shaking

The author is receiving on-line training on FPGA, so as to come to the end, it is an entry point in terms of level. When designing, it is found that it is very important to make some design summaries, which can help us clear our thinking and get a good review for future review. I've been studying altera FPGA before, and I'm not familiar with xi ...

Posted on Wed, 12 Jun 2019 10:20:33 -0700 by txmedic03

Asynchronous Reset and Synchronous Release Mechanism-Perfect Stability of the System

When I look back, I read two books and did a few minor projects. I watched some of the great gods chatting in QQ group. Sometimes I still put in a few sentences. It's normal that no one cares about a word. Sometimes they also help the netizens who are rookies to solve the problem. How embarrassing! In the words of the gods, they also draw a lit ...

Posted on Sat, 30 Mar 2019 19:06:28 -0700 by Otiose Dodge

Design of Multifunctional Digital Clock with verilog Based on basys2 (Rewrite)

Picture above before you say more         Preface Since learning FPGA, the only complete system that has ever been built is a multi-function digital table based on basys2. I remember that I had a lot of headaches when I did that. Finally, I used time to grind out a small system which was not very complete. At that time, I still had a full sens ...

Posted on Tue, 26 Mar 2019 07:27:29 -0700 by kiosklim

verilog Design Picture Display Based on LCDQC12864B Driven by basys2

Picture above before you say more   Preface When doing this experiment, I found a lot of information on the internet. It's all about using MCU to drive LCD display. It's really a lot easier to use MCU to drive LCD display. I remember when I asked questions in the learning and communication group of FPGA, I was instructed by my predecessors and ...

Posted on Tue, 26 Mar 2019 03:54:28 -0700 by tjhilder

Design of asynchronous fifo

Firstly, the key and difficult points of asynchronous FIFO design are analyzed. Finally, the detailed code is given. I. A brief explanation of FIFO The essence of FIFO is RAM, first in first out Important parameter: fifo depth (in short, how many data needs to be stored) fifo Bit Width (Bit Width per Data) FIFO has two kinds: synchronous and ...

Posted on Thu, 21 Mar 2019 01:12:52 -0700 by asmon

Verilog Learning Notes Simple Function Implementation (7)......... Interface Design (Parallel Input Serial Output)

Complex interface design is realized by using state machine. This is a converter that converts parallel data into serial output, using bi-directional bus output. This is derived from the reduction of EEPROM reader. Firstly, the characteristics of I2C bus are introduced. I2C bus (inter integrated circuit) two-way two-wire serial bus protocol is: ...

Posted on Thu, 21 Mar 2019 01:03:51 -0700 by inspireddesign

Verilog Learning Notes Simple Function Implementation (3)......... Synchronized Finite State Machine

There are many ways to describe a finite state machine in Verilog. The most common way to describe a finite state machine is to use always and case statements. The state transition diagram shown in the following figure represents a simple finite state machine: Figure: The graph shows a four-state state machine with input A and Reset, synchrono ...

Posted on Wed, 20 Mar 2019 19:45:27 -0700 by Dr.Flink

Static timing analysis - timing path

Time series analysis tools find and analyze all paths in the design. Each path has a start point and an end point. The starting point is the point at which the data is loaded by the clock in the design, while the ending point is the point at which the data is loaded by another time through the combinational logic. The starting point in the pat ...

Posted on Wed, 20 Mar 2019 11:00:27 -0700 by kickstart

Cross-Clock Domain Processing

Topic: How to deal with cross-clock domain in multi-clock domain design Single bit: Two-stage trigger synchronization (for slow to fast) Multi-bit: Using asynchronous FIFO, asynchronous dual-port RAM Handshake signal Gray Code Conversion Title: Writing Verilog code to describe signal transmission across clock domain, from slow clock doma ...

Posted on Sun, 27 Jan 2019 16:03:15 -0800 by timgolding