The realization of Verilog HDL traffic light

I really have nothing to do at home. I turned out the small experiment of EDA class in the last semester of my junior year, which is to design a traffic light for two lengzi. I can only flash at the set time, red light, green light, yellow light and turn signal;

  • Time of each light: Gee, I'm too lazy to write. There are all the programs in the back.
  • Chip: EP4CE6E22C8144 pin of FPGA and Cylone IV E series.
  • External clock: 1Hz

Here is the complete procedure of this small experiment:

module  traffic(
            input clk,
            output reg r1,
            output reg y1,
            output reg g1,
            output reg b1,
            output reg r2,
            output reg y2,
            output reg g2,
            output reg b2
            );
        parameter yellow_time = 5;
        parameter green_time  = 20;
        parameter blue_time = 10;
        reg [2:0] state;

        always @(posedge clk)
            case (state)
                0:      /*North South green, East West Red*/
                    begin
                        r1 <= 1'b0;
                        y1 <= 1'b0;
                        g1 <= 1'b1;
                        b1 <= 1'b0;
                        r2 <= 1'b1;
                        y2 <= 1'b0;
                        g2 <= 1'b0;
                       b2 <= 1'b0;
                    end
                1:      /*North South Yellow, East West Red*/
                    begin
                        r1 <= 1'b0;
                        y1 <= 1'b1;
                        g1 <= 1'b0;
                        b1 <= 1'b0;
                        r2 <= 1'b1;
                        y2 <= 1'b0;
                        g2 <= 1'b0;
                        b2 <= 1'b0;
                    end
                2:      /*North South left, East West Red*/
                    begin
                        r1 <= 1'b0;
                        y1 <= 1'b0;
                        g1 <= 1'b0;
                        b1 <= 1'b1;
                        r2 <= 1'b1;
                        y2 <= 1'b0;
                        g2 <= 1'b0;
                        b2 <= 1'b0;
                    end
                3:  /*North south red, East West Green*/
                    begin
                        r1 <= 1'b1;
                        y1 <= 1'b0;
                        g1 <= 1'b0;
                        b1 <= 1'b0;
                        r2 <= 1'b0;
                        y2 <= 1'b0;
                        g2 <= 1'b1;
                        b2 <= 1'b0;
                    end
                4:  /*North south red, East West Yellow*/
                    begin
                        r1 <= 1'b1;
                        y1 <= 1'b0;
                        g1 <= 1'b0;
                        b1 <= 1'b0;
                        
                        r2 <= 1'b0;
                        y2 <= 1'b1;
                        g2 <= 1'b0;
                        b2 <= 1'b0;
                    end
                
                
            default:    /*North south red, east west left*/
                begin
                    r1 <= 1'b1;
                    y1 <= 1'b0;
                    g1 <= 1'b0;
                    b1 <= 1'b0;
                    r2 <= 1'b0;
                    y2 <= 1'b0;
                    g2 <= 1'b0;
                    b2 <= 1'b1;
                end
            endcase
        
        always @(posedge clk)
            begin
                reg [4:0] count;
                begin
                    if(count == 0)
                        begin
                            if(state == 5)
                                state <= 0;
                            else 
                                state <= state +1;
                            case    (state)
                                0:
                                    count = yellow_time;
                                1:
                                    count = blue_time;
                                2:
                                    count =  green_time;
                                3:
                                    count = yellow_time;
                                4:
                                    count = blue_time;
                                default:
                                    count = green_time;
                            endcase
                        end
                    else
                        count = count - 1;              
                end             
            end 
endmodule

This is the pin configuration. It's all in the book. It's just that the sequence is always reversed, which makes me change it several times.

This is the last schematic

Tags: Verilog

Posted on Sat, 21 Mar 2020 09:05:09 -0700 by CJLeah